Cadence Announces 28nm Silicon Realization Toolset

Today, Cadence Systems announces at DesignCon 2011 the next step in their EDA360 vision: Cadence Silicon Realization. Silicon Realization is claimed to cover the entire scope of tools and capabilities required to get a design into silicon ? be it analog or digital IP block, an IP subsystem for an system-on-chip (SoC) or a completed IC or SoC, including the package in which the silicon sits.

The announcement focuses on Cadence’s approach to 28nm (nanometer) flow supports unique and pervasive design intent, abstraction, and convergence from Register Transfer Level (RTL) to Graphic Database System file format (GDSII), then through to packaging. Another way to think of this is to remember how good mother’s lemon pie was. Then go to your favorite search engine and look up recipes for lemon pie.

The ingredients are mostly similar. But, which one will make the lemon pie you want. Cadence Silicon Realization is a time saving recipe for building your SoC. The major parameters a chip design team has to consider are temperature, performance, power consumption, and of course price. Each is a factor that can delay the development process. The traditional approach was to design the hardware and then build the software applications to fit the chip.

There is now greater demand for semiconductor companies to provide application-ready platforms with hardware and software for each vertical market. When Apple introduced their first-generation iPhone, the chip creation world was shaken to its core. Apple showed that their huge sales, and therefore profits, were in having the software drive the development of the hardware. With the Apple iPad, a special version of the Samsung fabbed CPU was created to enhance the capabilities of the Apple operating system and the tablet’s software applications.

Cadence Silicon Realization is an end-to-end solution that starts with your application parameters and helps you produce the final chip to do that particular job. Cadence 28nm flow has special features to speed the design process and reduce the time to tape out and fabbing a wafer on the first pass.

Silicon Realization is eliminating the need for tradeoffs between complexity and advanced process nodes, the new flow optimizes complex design at 28 nanometers, providing a path (flow) for advanced SoC development to realize the cost benefits of smaller geometries. Key to the flow’s performance is a unified process of digital design, implementation, and verification based on intent, abstraction, and convergence.

According to the official press release, key features that enhance unified intent include:

  • complete, silicon-proven 28nm design rule intent (electrical, physical, DFM) with early, upfront tradeoff analysis, and a 2x improvement in routing runtime through intelligent via and pin-density optimizations
  • early clock topology intent capture and planning that uses physical information to intelligently optimize clock gating and balance clock trees throughout the design during synthesis

Features that enhance abstraction include:

  • breakthrough data abstraction technologies that enable entire blocks of logic to be modeled simply and accurately, and optimized across logical and physical domains, for giga-gate scalability and design productivity
  • support for hierarchical low-power and OpenAccess-based mixed-signal quick/detailed abstractions to enable rapid integration of IP and advanced SoCs

faster convergence is achieved through such features as:

  • a physically aware pre-mask functional ECO capability that automates difficult to implement functional ECOs, providing faster convergence and dramatically shortening the design cycle
  • a breakthrough architecture for in-design advanced analysis that provides ultra fast one-step signal integrity and timing analysis closure during the design flow for efficient design convergence
  • accurate full mixed-signal static timing analysis and timing-driven optimization to reduce iterations between analog and digital design teams
  • and new fully-integrated 3D-IC capabilities with unified intent, abstraction, and convergence spanning digital, full-custom, and package design, now enable optimized performance, size, cost and power.

After studying the key points above, who is using the Cadence approach? ARM is working with Cadence Silicon Realization for their latest Cortex A-15 28nm design. Some of the chip manufacturers include SilansysGlobalFoundriesTeledyneSTmicroelectronics, and other members of the Common Platform Alliance.

Spreadtrum Communications used the Cadence Silicon Realization process for their 40nm version low power TD-HSPA/TD-SCDMA multi-mode communication baseband processor. The chip was taped out with one-pass silicon success and is commercially available. David Desharnais, senior director for product marketing of Silicon Realization said:

Our unique Silicon Realization approach allows our customers to push their SoC designs to new levels in order to deliver the highest performance silicon for multimedia, communications and computing applications.

Taking advantage of high-bandwidth broadband, remote applications, and pricing on a time per use basis is something that is missing in the semiconductor manufacturing process. There are many hurdles to overcome for this idea to be realized. This model is being used in the hosted GPGPU cloud by Peer 1. The idea was discussed at the Common Platform Alliance afternoon roundtable. Maybe this will be the next step in the EDA and chip fabrication world.