Enterprise, Hardware

Intel Announces XEON Phi, 50-core 22nm Coprocessor


Today at the International Supercomputing Conference (ISC) 2012 in Hamburg, Germany, Intel announced their Knights Corner coprocessor, the first member of their XEON Phi family. Knights Corner is the next generation of their multi-core, parallel processing coprocessor for the HPC (High Performance Computing) race to be a contender in the TOP500 Supercomputing Sites.

 Knights Corner specifications

Knights Corner specifications

 1 Teraflop from coprocessor node of Intel's HPC cluster

1 Teraflops from coprocessor node of Intel’s HPC cluster

FLOPs (or flops or flop/s, for floating-point operations per second ) are a measurement of a computer’s performance (e.g., required by a given algorithm or computer program). Way back when scientists starting counting FLOPS, human nature obviously sprung into action and the race was on, for the ?mine is faster than yours? TOP500 Supercomputing fastest FLOPS trophy. The race escalated to teraflops which are computing speed equal to one -million million-floating-point operations per second. Then came petaflops at quadrillion (thousand trillion) floating point operations per second (a thousand teraflops or 2 to the 50th power FLOPS).

The TOP500 project ranks and details the 500 (non-distributed) most powerful computer systems known in the world. This is the most important ranking in the HPC world of applying advanced computational science and engineering to critical fields like renewable energy, genomics and biosciences, nuclear safety, weather studies, design and simulation to name a very few. Underlying the fastest FLOPS race is the fact players in the TOP500 rankings also make lots and lots of profit from their highly sophisticated reuse of existing technology.

From FLOPS to Petaflops
From FLOPS to Petaflops

Rajeeb Hazra, Vice-President Intel Architecture Group & GM Technical Computing, said last November they demonstrated the first silicon of the Intel Xeon Phi coprocessor, code named ?Knights Corner?. It produced an astounding teraflop of performance in a processor the size of your thumb, setting the industry on notice of the potential of many core architectures and providing a clear path of how we’ll get to the Petascale and Exascale era. This is the same amount of flops as the Number one supercomputer in 1997on the TOP500 list, dubbed ASCI Red. ASIC Red used thousands of processors and filled a room with cabinets to produce the same amount of performance. Knights Corner quickly got the nickname of ?Supercomputer on a Chip?.

Last year at ISC 2011, Intel announced MIC (Many Integrated Core) architecture. MIC was not an outstanding branding of their engineering ideas. So earlier this year, Intel decided to improve their Fabric Technology which provides the communications links for data flow between processors and I/O devices.

In January, they bought InfiniBand from Qlogic for $125 million. This gave them scalable technology which is used to connect servers in high-performance computing (HPC) environments. Then in April, Intel made a very brief announcement that they were acquiring Cray’s Aires Technology for their HPC programs. Diane Bryant, vice president and general manager of Intel’s Datacenter and Connected System Group said: "The acquisition of Cray’s industry-leading interconnect technology and expertise provides exceptional strategic assets that further enhance Intel’s HPC portfolio. We’re excited about the value this will allow us to bring to our customers."

This is the same Ms. Bryant who announced this spring the XEON E5/2600 server line. When asked about Intel losing out to AMD over Seamciro’s architecture and fabric Ms. Bryant said Intel "did look at SeaMicro’s fabric technology. There are probably very few people they didn’t come to and shop their solution to. We were not impressed. We declined and very soon after our competitor acquired them." There does seem to be a contradiction in some of Intel’s explanations about HPC, server fabric technology, and whose stuff works – moving right along.

The target market for XEON Phi and Knights Corner are big universities and National Labs who are existing Intel customers with HPC-style, X86-based applications.

Target market for XEON Phi family

Target market for XEON Phi family

Those folks have old X86 apps and they were interested in XEON Phi and Knights Corner because they won’t have to re-write their old stuff into GPGPU (general purpose Graphic Processor Unit) languages like Nvidia’s CUDA or open-source OpenGL. Probably the decision by Oak Ridge National Labs to not rewrite their X86 apps were driven more by budget justification problems than anything else. In other words, if your X86 coding ain’t broke, don’t rewrite it for a GPGPU, simply add a bigger "engine" like a Knights Corner node to your HPC cluster.

In our next article about Knights Corner and the XEON Phi family, we will investigate where they came from and what it really means in light of Intel’s successes in this year’s TOP500 HPC FLOPS race.