Communication between cores on a computer chip becomes more and more difficult as the number of cores or processing units increases. Maintaining cache coherence, ensuring cores locally stored copies of globally accessible data is up to date is a problem that one set of researchers claims to have solved.
A group led by Li-Shiuan Peh, MIT Singapore Research Professor of Electrical Engineering and Computer Science, brought a 36-core network-on-a-chip to the International Symposium on Computer Architecture. Her team’s experimental design uses an Internet like communication network to manage local memory stores. Each core has an associated router where data travels between cores in packets of a fixed size.
Busses function successfully in most complex System on Chip (SoC) Silicon designs. However, cores connected by a bus stumble when the number of cores increases because the cores which do not have access to the bus at any given time sit idle. Bhavya Daya, an MIT graduate student in electrical engineering and computer science, and first author of the paper, says “Snoopy [a cache coherence protocol] intrinsically relies on ordered interconnects which do not scale well.”
Still, this design works nicely managing data. Each core has its own cache which it sends back to memory. When a core needs some particular data, it sends a request to all the other cores, and the one with the specific data ships it back to the requesting core. With the network-on-a-chip design, however, the inherent ordering that the snoopy protocol uses is impaired.
To overcome this failure, Peh’s group equipped their chips with a second network, which shadows the first. The snoopy protocol still works because a hierarchical ordering simulates the chronological ordering of requests sent over a bus.
Daya wants to prove the accuracy of the group’s theoretical projections. She plans to load the chips with a version of the Linux operating system, modified to run on 36 cores, and evaluate the performance of real applications. Thereafter, she will release blueprints for the chip, written in the hardware description language Verilog, as open-source code encouraging others to test and increase its viability.