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Linley Processor Conference – ARM Sweeps Next-Gen Processor Designs


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?Shift to ARM Becomes a Stampede? set the tone of Linley Gwenapp?s opening keynote address for the ?Linley Processor Conference? being held this week in Santa Clara, CA. He went on to note that the 64-bit ARMv8 ISA has opened new markets that now include servers, networking and communications for the company. Further, ?We do not believe [that a] dual-architecture strategy will endure? ? [it is] too expensive to validate CPU and Software of two ISA?s. Gwenapp predicted that although ARM has only a toehold in the network processor marketplace that the 64-bit designs just now starting will take 5-10 years of shipments before a full conversion to the ARM architecture is complete.

Broadcom Announces 64-bit ARMv8
The opening keynote was immediately followed by Broadcom Corporation?s [NASDAQ: BRCM] announcement of a 16 nm FinFET process – 64-bit ARMv8 based SoC for servers and communications. Broadcom signaled that they are shifting a wide array of products away from MIPS to ARM.

2013 Market share – expected to shift to ARM & x86 from PowerPC dominant role.

(Source: The Linley Group)

Broadcom showed a design that includes a quad-issue, quad-threaded, out-of-order ARMv8 processor designed in a 16 nm FinFET process capable of 3 GHz operation. Broadcom would not commit to a shipment date for the design ? though sources agree that the device will probably not ship until late 2014 at the earliest. Several analysts confided that the company would be lucky to see it ship in any volumes prior to 2016.
In sidebar conversations, the discussion centered on why Broadcom would announce so early in the design cycle ? seen clearly as a competitor to Intel?s Xeon a more apt caption to the announcement would have been ?to ARMs?.

Broadcom NFV Partnership with ARM ? Standardization Efforts
One of the conference themes was the development of open standards for Network Function Virtualization (NFV) support for software environments. Broadcom?s partnership with ARM aims to develop a portable software environment allowing customers a seamless migration of existing designs based on XLP II multi-core processors to the new ARMv8 processor architecture thus preserving their software investment.

The work will be under the auspices of Linaro, a not-for-profit (NFP) engineering organization that consolidates and optimizes open source software for the ARM architecture. Standardization efforts will occur under ETSI, the European Telecommunications Standards Institute, which produces globally applicable standards for Information and Communications Technologies (ICT), including fixed, mobile, radio, converged, broadcast and internet technologies.

Hybrid Memory Cube & Search Function in Memory
The demand for a cost effective higher bandwidth solution is a never-ending story for network processors. Until now, the high performance packet buffer has been best served by the RLDRAM supplied by Micron. Micron presented their version of the Hybrid Memory Cube, now sampling, as a ?Revolutionary Shift? solving boandwidth, power, latency, form factor and lower total cost of ownership issues. Their roadmap extends through a data delivery rate of 8Tbs (32BBytes).

Micron [NASDAQ:MU] is targeting application of the HMC to the 400Gbps Packet Buffer Memory subsystem for 100GbE (x4) net controllers. Micron also made an interesting point that although the Hybrid Memory Cube Consortium has over 100 adopters to date – the number had doubled in 2013 alone from 2012 and a number of companies, although members, requested their names remain unpublished from the list.

Micron is currently sampling the 2-GByte device and will begin shipping the 4-GByte device in the summer of 2014.
Mosys showed their second generation – architecture bandwidth engine with intelligent memory macros. Included on the device is the capability to perform Atomic Read-Modify-Write operations improving overall line card performance.

Xel Technology, Inc., (Beijing) presented a search function memory that effectively replaces the TCAM (ternary content addressable memory) function in networking. In questions from the audience it became apparent that Xel has already established design wins. Again, this places a search function on DRAM silicon that provides necessary performance boost, dramatically increases CAM memory depth while achieving acceptable cost.

BSN Take
Processor battles began with Intel?s 4004 – things have gotten exponentially more complex since then. The 64-bit ARMv8 appears to be a formidable competitor to Intel?s Xeon position ? but it does not yet exist as a shippable product. A lot of water will pass under the bridge before shipments begin on the 64-bit ARMv8 processors though the ball does seem to be firmly in the court of ARM Holdings PLC currently.

16 nm FinFET production is a paper target that has little capital expenditure going towards making it realizable outside of Intel and Samsung (and a trickle at TSMC). It is these type of investment realities that need to be settled before anyone gets overly excited about something that looks (best scenario) to be sampling in two years time.

Micron?s HMC presentation provided interesting feedback in that many feel the cost will be too high, similar to what Micron is charging for the RLDRAM. A problem for the HMC is that each vendors cube will be specific to that vendor (as per our current understanding) making them non-interchangeable or more pointedly sole sourced devices.
Formerly, non-second sourced devices had little chance of succeeding against supply chain management rules requiring a recognized second source. Newly introduced items will be sole sourced as the memory industry completes its current consolidation. Many in the user community are uncomfortable with the situation though they have come to accept the situation due to their need for performance.

One of the more interesting questions that came up was asked of Micron ? whether a certain amount of logic intelligence could be applied to the HMC?s interposer logic to perform TCAM search functions and intelligent memory macros as presented by Xel and Mosys respectively. Micron replied was that this was entirely possible?,