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Soft Machines Unveils VISC CPU Architecture at Linley

Soft Machines VISC Architecture Soft Machines VISC Architecture

Soft Machines is a startup that today is coming out of their stealthmode status into the public at the Linley Processor Conference.

Soft Machines is a company that has been around since 2006 and employs 250 people on three different continents, all with the expressed goal of working together to deliver their new VISC CPU architecture. The company’s CEO, Mahesh Lingareddy, comes from Intel (NASDAQ: INTC) as did its co-founder Mohammad Abdallah, which would explain the company’s focus on single threaded performance. Soft Machines has raised over $125 million from various funding sources including multiple angel investors, multiple sovereign wealth funds and semiconductor companies, including AMD (NYSE: AMD).

The core of this technology is essentially the virtualization of multiple CPU cores into a single virtual core that enables much higher single threaded performance. That is why they call this technology a VISC CPU architecture as opposed to the RISC and CISC architectures that exist today. As you can see from the image above, there is a very specific way that they achieve this virtualized CPU architecture who’s goal is not only to abstract the cores but to also abstract the ISA, as they claim to be able to run virtually any ISA on their cores if needed, which is how they are able to demonstrate that they are running Android ICS (not Kit Kat) on their demonstration machine today at Linley.





With this architecture, they are able to essentially abstract whatever ISA is being run and then virtualize it so that they can run it on their virtual cores, which will then decide how many threads are needed and how many virtual cores need to be allocated. So, you can have a dual core or a quad core (physical) processor, but then you may only have one or two virtual cores depending on the workload being put on the processor. One metric we haven’t seen or know about is memory bandwidth, we still don’t know what kind of bandwidth they’re able to get with their cache or what frequency their DDR3 is capable of running at.



They are currently running a test setup at the Linley CPU Conference, and we’ve found out that their target performance is currently low power mobile SoCs, but that they are also capable of scaling all the way up to high performance CPUs. They are showing a mobile SoC that is designed to illustrate their power efficiency and the SoC is being used as a test vehicle and they are also fabbing with TSMC at their 28nm process. This SoC, according to them, has 1 billion transistors with less than 20% of the SoC’s transistors being attributed to their own core IP. So, they’ve essentially already shown that their cores not only work, but can be integrated into an SoC and work. here are some of the performance figures.


According to the performance figures provided, using SPEC 2006 IPC, they are running much faster than almost all of their competition in single threaded performance. Do keep in mind that the demonstration that they are currently showing is a dual core implementation running as one virtual core. In this prototype VISC implementation, they are able to get a score of 2.1 versus all other single core implementations. Obviously, these numbers are going to be designed to make them look as good as possible, but there’s no denying the promise that they have. In fact, they are already working with multiple customers to integrate their core IP into SoCs and should have customer silicon out next year. Below, you can see their test setup at Linley.


Test Setup

Test Setup

Their focus is not only single threaded IPC, but also to ensure that power utilization is also much lower, in their SPEC/Watt comparison you can see that they are showing fairly significant gains for their dual core processor at the same wattage or lower wattage. The real question will be whether or not their architecture gains enough traction among CPU and SoC vendors that they actually become relevant. After all, MIPS is having a very hard time competing with ARM and Intel as it is already and they’re the ‘third’ architecture out there right now. If we have a fourth, are SoC vendors really going to want to have their resources spread across so many different architectures?

VISC Single Thread SPEC per Watt

VISC Single Thread SPEC per Watt

As you can see, they already have working silicon, which is a huge step forward for any new architecture hoping to present itself as a viable alternative to existing architectures. The fact that they aren’t trying to build their own CPUs and sell those directly is very likely a smart idea, as both ARM and Imagination Technologies (MIPS) are licensing their cores out to SoC vendors willing to work with their IP. What will be important to see is how Soft Machines will support its customers with software and development and ensure that the end consumer has no idea what SoC is running under the hood and that the SoC vendor is happy with the performance and battery life of their devices. Increasingly these days, software is becoming a more and more important part of whether or not your hardware will gain adoption, so if the guys at Soft Machines have a solid software team and strategy, they may have a chance. Because there’s no denying that virtually everyone is going to be skeptical about a new CPU architecture gaining any traction.

Soft Machines also has tons of patents already filed and granted around its VISC architecture that you can look into yourself if you’re skeptical or want to know more details about the new architecture.